FEC Software Decoders Hall of Fame

This page presents a Channel Coding Software Decoders "Hall of Fame". It allows to see at a glance what has been achieved, what can be expected from today software decoders, and easily compare their respective characteristics. For now, three wide code families are considered: the Turbo codes (LTE, LTE-Advanced, CCSDS, etc.), the Low-Density Parity-Check (LDPC) codes (5G, Wi-Fi, WiMAX, CCSDS, WRAN, DVB-S2, etc.), and the more recently introduced Polar codes (5G).

All the presented results, collected from the state-of-the-art research papers published in the field, consider a BPSK (Bit Phase-Shift Keying) modulation/demodulation and an AWGN (Additive White Gaussian Noise) channel.

This Hall of Fame strives to present results as fairly as possible: for example, early termination criteria are not taken into consideration while computing throughput, in order to compare raw performances using a consistent method. It remains possible, however, for typos/glitches/mistakes to have inadvertantly made it to the scoreboard. In that eventuality, do not hesitate to contact us. If you would like to have your decoder listed as well in the Hall of Fame: please send us the corresponding research paper references, and we will be delighted to add them.

In blue, the results simulated or reproducible with AFF3CT: our Open-source communication chain dedicated to the Forward Error Correction (FEC) simulations.

Last update: 2021-05-17.

Do you like the FEC Software Decoders Hall of Fame? Is it useful in your research works? If yes, you can thank us by citing the following journal article: A. Cassagne et al., “AFF3CT: A Fast Forward Error Correction Toolbox!,“ SoftwareX, 2019.  

Maximum A Posteriori (MAP) - 8-state trellis

Work Year Platform Implem. Pre. Inter K R i Lat. Thr. NThr. TNDC Ed
[1] 2010 Tesla C1060 ML-MAP 32 100 6144 1/3 5 76800 8.0 6.7 0.021 29851
[2] 2011 GTX 470 ML-MAP 32 100 6144 1/3 5 20827 29.5 24.6 0.045 8740
[3] 2011 i7-960 ML-MAP 16 1 1008 1/3 8 138 7.3 9.7 0.380 13402
[4] 2012 9800 GX2 ML-MAP 32 1 6144 1/3 5 3072 2.0 1.7 0.0043 115882
[5] 2012 Tesla C2050 L-MAP 32 32 11918 1/3 5 108965 3.5 2.9 0.0057 85172
[6] 2012 X5670 EML-MAP 8 6 5824 1/3 3 157 222.6 111.3 0.396 854
[7] 2013 GTX 480 EML-MAP 32 1 6144 1/3 6 50 122.8 122.8 0.183 2036
[8] 2013 GTX 580 ML-MAP 32 1 6144 1/3 6 1660 3.7 3.7 0.0047 63946
[9] 2013 GTX 550 Ti EML-MAP 32 1 6144 1/3 6 72 85.3 85.3 0.247 1360
[10] 2013 GTX 680 EML-MAP 32 16 6144 1/3 6 2657 37.0 37.0 0.024 5270
[10] 2013 i7-3770K EML-MAP 16 4 6144 1/3 6 323 76.2 76.2 0.680 1011
[11] 2014 Tesla K20c ML-MAP 32 1 6144 1/3 5 1097 5.6 4.7 0.0026 47872
[12] 2014 GTX 580 BR-SOVA 8 4 6144 1/3 5 192 127.8 106.5 0.135 2291
[13] 2016 GTX 680 EML-MAP 32 1 6144 1/3 7 817 8.2 9.6 0.0062 20313
[14] 2016 2xE5-2680v3 EML-MAP 16 192 6144 1/3 6 2657 443.7 443.7 0.924 541
[14] 2016 2xE5-2680v3 EML-MAP 8 384 6144 1/3 6 3293 716.4 716.4 0.746 335
[15] 2019 2xE5-2680v3 EML-MAP 8 24 6144 1/3 6 84 1735.0 1735.0 0.904 138

Fully-Parallel Turbo Decoder (FPTD) - 8-state trellis

Work Year Platform Implem. Pre. Inter K R i Lat. Thr. Ed
[13] 2016 GTX 680 FPTD 32 1 6144 1/3 36 403 18.7 10428

References

  1. M. Wu, Y. Sun, and J. R. Cavallaro, “Implementation of a 3GPP LTE Turbo Decoder Accelerator on GPU,” in Proceedings of the IEEE International Workshop on Signal Processing Systems (SiPS), October 2010.
  2. M. Wu, Y. Sun, G. Wang, and J. R. Cavallaro, “Implementation of a High Throughput 3GPP Turbo Decoder on GPU,” Springer Journal of Signal Processing Systems (JSPS), September 2011.
  3. L. Huang and Y. Luo and H. Wang and F. Yang and Z. Shi and D. Gu, “A High Speed Turbo Decoder Implementation for CPU-Based SDR System,” in Proceedings of the IEEE International Conference on Communication Technology and Applications (ICCTA), October 2011.
  4. D. Yoge and N. Chandrachoodan, “GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications,” in Proceedings of the IEEE International Conference on VLSI Design (VLSID), January 2012.
  5. S. Chinnici and P. Spallaccini, “Fast Simulation of Turbo Codes on GPUs,” in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC), August 2012.
  6. S. Zhang, R. Qian, T. Peng, R. Duan, and K. Chen, “High Throughput Turbo Decoder Design for GPP Platform,” in Proceedings of the IEEE International Conference on Communications and Networking in China (CHINACOM), August 2012.
  7. J. Xianjun, C. Canfeng, P. Jaaskelainen, V. Guzma, and H. Berg, “A 122Mb/s Turbo Decoder using a Mid-Range GPU,” in Proceedings of the IEEE International Wireless Communications and Mobile Computing Conference (IWCMC), July 2013.
  8. X. Chen, J. Zhu, Z. Wen, Y. Wang, and H. Yang, “BER Guaranteed Optimization and Implementation of Parallel Turbo Decoding on GPU,” in Proceedings of the IEEE International Conference on Communications and Networking in China (CHINACOM), August 2013.
  9. C. Liu, Z. Bie, C. Chen, and X. Jiao, “A Parallel LTE Turbo Decoder on GPU,” in Proceedings of the IEEE International Conference on Communication Technology (ICCT), November 2013.
  10. M. Wu, G. Wang, B. Yin, C. Studer, and J. R. Cavallaro, “HSPA+/LTE-A Turbo Decoder on GPU and Multicore CPU,” in Proceedings of the IEEE Asilomar Conference on Signals, Systems, and Computers (ACSSC), November 2013.
  11. Y. Zhang and Z. Xing and L. Yuan and C. Liu and Q. Wang, “The Acceleration of Turbo Decoder on the Newest GPGPU of Kepler Architecture,” in Proceedings of the IEEE International Symposium on Communications and Information Technologies (ISCIT), September 2014.
  12. R. Li, Y. Dou, J. Xu, X. Niu, and S. Ni, “An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014.
  13. A. Li, R. G. Maunder, B. M. Al-Hashimi, and L. Hanzo, “Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit,” IEEE Access, June 2016.
  14. A. Cassagne, T. Tonnellier, C. Leroux, B. Le Gal, O. Aumage, and D. Barthou, “Beyond Gbps Turbo Decoder on Multi-Core CPUs,” in Proceedings of the IEEE International Symposium on Turbo Codes and Iterative Information Processing (ISTC), September 2016.
  15. B. Le Gal and C. Jégo, “Low-latency and High-throughput Software Turbo Decoders on Multi-core Architectures,” Springer Annals of Telecommunications, August 2019.