# Channel Coding Software Decoders Hall of Fame

This page presents a Channel Coding Software Decoders "Hall of Fame". It allows to see at a glance what has been achieved, what can be expected from today software decoders, and easily compare their respective characteristics. For now, three wide code families are considered: the Turbo codes (LTE, LTE-Advanced, CCSDS, etc.), the Low-Density Parity-Check (LDPC) codes (Wi-Fi, WiMAX, CCSDS, WRAN, DVB-S2, etc.), and the recently introduced Polar codes (candidates for 5G).

All the presented results, collected from the state-of-the-art research papers published in the field, consider a BPSK (Bit Phase-Shift Keying) modulation/demodulation and an AWGN (Additive White Gaussian Noise) channel.

This Hall of Fame strives to present results as fairly as possible: for example, early termination criteria are not taken into consideration while computing throughput, in order to compare raw performances using a consistent method. It remains possible, however, for typos/glitches/mistakes to have inadvertantly made it to the scoreboard. In that eventuality, do not hesitate to contact us. If you would like to have your decoder listed as well in the Hall of Fame: please send us the corresponding research paper references, and we will be delighted to add them.

In blue, the results simulated or reproducible with AFF3CT: our Open-source communication chain dedicated to the Forward Error Correction (FEC) simulations.

Last update: 2017-10-24.

Belief Propagation (BP)
Work Year Platform Implem. Pre. Inter Code $i$ $\mathrm{Lat.}$ $\mathrm{Thr.}$ $\mathrm{NThr.}$ $\mathrm{TNDC}$ ${E}_{d}$
[1] 2008 CELL F-MS 8 96 (1248, 624) 25 3653 32.8 16.4 0.052 6098
[2] 2008 8800 GT F-SPA+ 32 1 (4096, 2048) 6 467000 0.01 0.001 0.000006 105000000
[3] 2009 8800 GTX F-SPA 32 - (1908, 1696) 50 - 0.08 0.08 0.0005 2200000
[4] 2011 CELL F-OMS 8 1 (960, 480) 15 74 13.0 3.9 0.0095 51282
[5] 2011 Tesla C1060 F-LSPA 32 1 (8000, 4000) 50 8638 0.92 0.92 0.0029 217391
[6] 2011 Tesla C2050 F-MS 8 16 (64800, 21600) 30 13275 78.1 46.86 0.091 5271
[7] 2011 8800 GTX F-SPA 8 - (8000, 4000) 50 - 10.1 10.1 0.058 17426
[7] 2011 CELL F-SPA 32 24 (1024, 512) 50 1719 14.3 14.3 0.181 13986
[7] 2011 2xE5530 F-SPA 32 1 (8000, 4000) 50 13115 0.61 0.61 0.0079 262295
[8] 2011 GTX 285 F-SPA+ 32 1 (2304, 1152) 15 1097 2.1 0.63 0.0018 323810
[9] 2011 GTX 470 F-LSPA+ 32 300 (1944, 972) 50 57743 10.1 10.1 0.018 21287
[10] 2011 GTX 470 F-LSPA 32 224 (2304, 1152) 10 10533 49.0 9.8 0.018 21939
[11] 2012 HD 5870 F-MS 8 500 (8000, 4000) 10 22222 180.0 36.0 0.075 5222
[11] 2012 Tesla C2050 F-MS 8 500 (8000, 4000) 10 20000 200.0 40.0 0.078 6175
[12] 2012 GTX 480 F-SPA+ 32 1 (2048, 1723) 50 426 4.8 4.8 0.0071 52083
[13] 2012 Tesla C2050 F-MS 8 128 (16200, 8100) 50 26083 79.5 79.5 0.154 3107
[13] 2012 i7-950 F-MS 8 128 (16200, 8100) 50 113934 18.2 18.2 0.093 7143
[14] 2013 i7-3960X F-NMS+ 8 12 (9216, 4608) 10 1202 92.0 18.4 0.058 7065
[15] 2013 i7-2600K L-OMS 8 1 (524280, 262140) 5 17420 30.1 3.0 0.055 31667
[16] 2013 Cortex-A9 F-MS 8 128 (16200, 8100) 20 592457 3.5 1.4 0.014 2857
[17] 2013 GTX TITAN F-NMS+ 32 50 (2304, 1152) 10 1266 304.2 60.8 0.027 4112
[17] 2013 GTX TITAN F-NMS+ 32 6 (2304, 1152) 10 207 66.8 13.4 0.006 18657
[18] 2013 GTX 580 CL-MS 8 1024 (2304, 1152) 5 3322 710.2 142.0 0.180 1718
[19] 2014 GTX 660 Ti F-SPA 8 12544 (8000, 4000) 50 954100 105.2 105.2 0.085 1426
[20] 2014 GTX 660 HL-OMS 8 16384 (1944, 972) 10 34362 926.9 185.4 0.049 755
[21] 2016 i7-4960HQ HL-NMS+ 8 128 (2304, 1152) 50 1359 217 217 0.500 217
[22] 2016 GTX 470 PL-MS 32 256 (1944, 972) 10 9739 51.1 10.2 0.019 21078
Linear Programming (LP)
Work Year Platform Implem. Pre. Inter Code $i$ $\mathrm{Lat.}$ $\mathrm{Thr.}$ $\mathrm{NThr.}$ $\mathrm{TNDC}$ ${E}_{d}$
[23] 2016 i7-4960HQ F-ADMM 32 4 (2304, 1152) 8 1511 6.1 0.98 0.009 47959
[24] 2016 i7-4960HQ HL-ADMM 32 32 (2304, 1152) 100 13755 5.4 10.8 0.099 4352

## References

1. G. Falcao, V. Silva, L. Sousa, and J. Marinho, “High coded data rate and multicodeword WiMAX LDPC decoding on the Cell/BE,” Electronics Letters, vol. 44, no. 24, pp. 1415-1417, 2008.
2. S. Wang, S. Cheng, and Q. Wu, “A parallel decoding algorithm of LDPC codes using CUDA,” in Signals, Systems and Computers conference, 2008.
3. G. Falcao, S. Yamagiwa, V. Silva, and L. Sousa, “Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach,” J. of Computer Science And Technology, vol. 24, pp. 913-924, 2009.
4. J. Zhao, M. Zhao, H. Yang, J. Chen, X. Chen, and J. Wang, “High performance LDPC decoder on CELL BE for WiMAX system,” in Proceedings of the CMC Conference, 2011, pp. 278-281.
5. C-C. Chang, Y-L. Chang, M-Y. Huang and B. Huang, “Accelerating Regular LDPC Code Decoders on GPUs,” IEEE J-STARS, vol. 4, no. 3, pp. 653-659, 2011.
6. G. Falcao, J. Andrade, V. Silva, and L. Sousa, “GPU-based DVBS2 LDPC decoder with high throughput and fast error floor detection,” Electronics Letters, vol. 47, no. 9, pp. 542-543, 2011.
7. G. Falcao, L. Sousa, and V. Silva, “Massively LDPC decoding on multicore architectures,” IEEE Transactions on Parallel and Distributed Systems, vol. 22, no. 2, pp. 309-322, 2011.
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14. X. Pan, X. fan Lu, M. qi Li, and R. fang Song, “A high throughput LDPC decoder in CMMB based on virtual radio,” in Proceedings of the WCNC Workshop, 2013, pp. 95-99.
15. X. Han, K. Niu, and Z. He, “Implementation of IEEE 802.11n LDPC codes based on general purpose processors,” in Proceedings of the ICCT Conference, 2013, pp. 218-222.
16. S. Gronroos and J. Bjorkqvist, “Performance evaluation of LDPC decoding on a general purpose mobile CPU,” in Proceedings of the GlobalSIP Conference, 2013, pp. 1278-1281.
17. G. Wang, M. Wu, B. Yin, and J. R. Cavallaro, “High throughput low latency LDPC decoding on GPU for SDR systems,” in Proceedings of the IEEE GlobalSIP Conference, 2013, pp. 1258-1261.
18. R. Li, J. Zhou, Y. Dou, S. Guo, D. Zou and S. Wang, “A multi-standard efficient column-layered LDPC decoder for software defined radio on GPUs,” in Proceedings of the SPAWC Workshop, 2013, pp. 724-728.
19. Y. Lin and W. Niu, “High throughput LDPC decoder on GPU,” IEEE Communications Letters, vol. 18, no. 2, pp. 344-347, 2014.
20. B. Le Gal, C. Jego, and J. Crenne, “A high throughput efficient approach for decoding LDPC codes onto GPU devices,” IEEE Embedded Systems Letters, vol. 6, no. 2, pp. 29-32, 2014.
21. B. Le Gal and C. Jego, “High-Throughput Multi-Core LDPC Decoders Based on x86 Processor,” IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 5, pp. 1373-1386, 2016.
22. B. C. Lai, C. Y. Lee, T. H. Chiu, H. K. Kuo and C. K. Chang, “Unified Designs for High Performance LDPC Decoding on GPGPU,” IEEE Transactions on Computers, vol.PP, no.99, pp.1-1, 2016.
23. I. Debbabi, N. Khouja, F. Tlili, B. Le Gal, C. Jego, “Multicore Implementation of LDPC Decoders based on ADMM Algorithm,” in Proceedings of the 41st IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP’16), pages 971-975, Shangai, China, 20-25 March 2016.
24. I. Debbabi, B. Le Gal, N. Khouja, F. Tlili, and C. Jego, “Real time LP decoding of LDPC codes for applications requiring high correction performances,” IEEE Wireless Communications Letters, vol. 5, no. 6, pp. 676-679, 2016.